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MAX8930
WLED Charge Pump, RGB, OLED Boost,
LDOs with ALC and CAI
SDA
t BUF
t LOW
t SU ,DAT
t HD,DAT
t SU,STA
t HD,STA
t SU,STO
SCL
t HD,STA
t R
t HIGH
t F
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 11. START and STOP Conditions
SDA
SCLK
MASTER
TRANSMITTER/
RECEIVER
Figure 12. I 2 C Master and Slave Configuration
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
I 2 C Bit Transfer
One data bit is transferred for each clock pulse. The data
on SDA must remain stable during the high portion of
the clock pulse as changes in data during this time are
interpreted as a control signal.
I 2 C START and STOP Conditions
Both SDA and SCL remain high when the bus is not
busy. A high-to-low transition of SDA, while SCL is high is
defined as the START (S) condition. A low-to-high transi-
tion of the data line while SCL is high is defined as the
STOP (P) condition.
Maxim Integrated
I 2 C System Configuration
A device on the I 2 C bus that generates a message is
called a transmitter and a device that receives the mes-
sage is a receiver. The device that controls the message
is the master and the devices that are controlled by the
master are called slaves.
I 2 C Acknowledge
The number of data bytes between the START and STOP
conditions for the transmitter and receiver are unlimited.
Each 8-bit byte is followed by an acknowledge bit. The
acknowledge bit is a high-level signal put on DATA by
the transmitter during which time the master generates an
extra acknowledge related clock pulse. A slave receiver
that is addressed must generate an acknowledge after
each byte it receives. Also, a master receiver must gen-
erate an acknowledge after each byte it receives that
has been clocked out of the slave transmitter.
33
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